Domino (or dynamic) logic circuits are often employed in high performance systems. For example, consider a computer system, such as that illustrated in FIG. 1. In FIG. 1, microprocessor die 102 comprises many sub-blocks, such as arithmetic logic unit (ALU) 104 and on-chip cache 106. Microprocessor 102 may also communicate to other levels of cache, such as off-chip cache 108. Higher memory hierarchy levels, such as system memory 110, are accessed via host bus 112 and chipset 114. In addition, other off-chip functional units, such as graphics accelerator 116 and network interface controller (NIC) 118, to name just a few, may communicate with microprocessor 102 via appropriate busses or ports.
Some or all of the functional units making up a computer system as described above may comprise domino logic circuits. Some of these domino circuits may employ clock gating, where they are put into an inactive state when not needed so as to reduce wasted power. However, for deep sub-micron process technology, wasted power due to current leakage may nevertheless present problems in clock gated domino circuits if not properly taken into account. Various techniques have been proposed for reducing leakage current, such as, for example, using dynamic threshold scaling or providing multiple supply voltages. Such techniques often introduce a performance penalty or additional hardware cost and complexity. The use of long channel length transistors in clock-gated domino circuits has also been contemplated for reducing current leakage. However, to the best of our knowledge, such previously considered techniques for using long channel length transistors in clock gated domino logic circuits have introduced a penalty in performance.